Method and apparatus for sequencing power in a photodetector circuit

ABSTRACT

A circuit for use with a photodetector includes multiple switches, a comparator, and a capacitor. The photodetector receives a first voltage and a second voltage at first and second nodes, respectively. The first voltage is higher than the second voltage. The capacitor is connected to the first node. During a power up sequence, the capacitor is charged to the first voltage. The comparator detects when the voltage at the first node reaches a predetermined threshold and in response causes a switch to close so that the second node can receive the second voltage. In a power down sequence, the first and second nodes are allowed to discharge, with the capacitor slowing the discharge of the first node. The comparator detects when the voltage at the first node reaches a predetermined threshold and in response causes another switch to short the second node to ground.

TECHNICAL FIELD

[0001] This disclosure relates generally to photodetector circuits, andin particular but not exclusively, relates to power-up and power-downcircuits for use with photodetector circuits.

BACKGROUND

[0002] Photodetector circuits are widely used in optical receiverapplications. One type of photodetector is implemented with a photodiodeand a trans-impedance pre-amplifier. In operation, the photodiode isreverse biased, with light causing the photodiode to generate a reversecurrent that is amplified by the pre-amplifier. The pre-amplifiertypically includes a gain resistor that is connected between the inputand output leads of the pre-amplifier.

[0003] Such photodetector circuits used in fiber optic applications arerelatively expensive. In powering these photodetector circuits, careshould be taken to prevent forward biasing of the photodiode because thephotodiode can be damaged when it conducts relatively large currents.

BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Non-limiting and non-exhaustive embodiments of the presentinvention are described with reference to the following figures, whereinlike reference numerals refer to like parts throughout the various viewsunless otherwise specified.

[0005]FIG. 1 is a block diagram illustrating a power sequencing circuitaccording to one embodiment of the present invention.

[0006]FIG. 2 is a timing diagram illustrating voltages at selectedpoints of the power sequencing circuit of FIG. 1.

[0007]FIG. 3 is a diagram illustrating the relative timing of the outputvoltages of the power sequencing circuit of FIG. 1.

[0008]FIG. 4 is a schematic diagram illustrating an implementation ofthe power sequencing circuit of FIG. 1, according to one embodiment ofthe present invention.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

[0009] Embodiments of a method and apparatus for sequencing power in aphotodetector circuit are described herein. In the followingdescription, numerous specific details are set forth (such as switches,scalers and threshold detectors) to provide a thorough understanding ofembodiments of the invention. One skilled in the relevant art willrecognize, however, that the invention can be practiced without one ormore of the specific details, or with other methods, components,materials, etc. In other instances, well-known structures, materials, oroperations are not shown or described in detail to avoid obscuringaspects of the invention.

[0010] Reference throughout this specification to “one embodiment” or“an embodiment” means that a particular feature, structure, orcharacteristic described in connection with the embodiment is includedin at least one embodiment of the present invention. Thus, theappearances of the phrases “in one embodiment” or “in an embodiment” invarious places throughout this specification are not necessarily allreferring to the same embodiment. Furthermore, the particular features,structures, or characteristics may be combined in any suitable manner inone or more embodiments.

[0011]FIG. 1 illustrates a photodetector system 100, according to oneembodiment of the present invention. In this embodiment, photodetectorsystem 100 includes a power sequencing circuit 102 and a photodetectorunit 104. In one embodiment, photodetector unit 104 is a commerciallyavailable module or integrated circuit die that is separate from powersequencing circuit 102. In other embodiments, power sequencing circuit102 and photodetector unit 104 may be integrated on the same die. Aspreviously described, photodetector unit 104 includes a photodiode (notshown) that can be damaged if forward biased and a pre-amplifier (notshown) for amplifying the output current of the photodiode. As will bedescribed below, power-sequencing circuit 102 is used to control thevoltages provided to power photodetector unit 104.

[0012] In addition, power-sequencing circuit 102 includes a capacitor108, switches 111-114, a voltage scaler 116, and a threshold detector118. In this embodiment, voltage scaler 116 outputs a voltage having alevel that is a scaled version of an input voltage. For example, in oneembodiment, voltage scaler 116 is implemented using a standard voltagedivider circuit. In other embodiments, scaler 116 may be omitted,depending on how threshold detector 118 is implemented. Thresholddetector 118 is configured to detect whether the scaled voltage isgreater or less than a preselected voltage level or threshold. However,in other embodiments, threshold detector 118 may have hysteresis.

[0013] The elements of power sequencing circuit 102 are interconnectedas follows. Switch 111 has first, second and control terminalsrespectively connected to a line 120 (to receive a voltage V1), a line122 and a line 124 (to receive a control signal POR). Switch 112 hasfirst, second and control terminals respectively connected to a line 126(to receive a voltage V2), a line 128, and to line 124. Voltages V1 andV2 are provided by voltage sources (not shown) external to system 100.In one embodiment, voltages V1 and V2 are twelve and eight volts,respectively. In other embodiments, voltages V1 and V2 may be different,depending on the requirements of photodetector unit 104. Voltage V1 istypically higher than voltage V2 so that the photodiode of photodetectorunit 104 cannot be forward biased during operation (i.e., the photodiodemay be damaged if forward biased).

[0014] In this embodiment, switches 111, 112, and 114 are designed sothat they are turned on when their control terminals receive logic highlevel signals. In contrast, in this embodiment, switch 113 is designedto close when its control terminal receives a logic low level signal.

[0015] Continuing with the description of the interconnection, thresholddetector 118 has an input terminal connected to a line 132 (i.e., theoutput terminal of scaler 116. Scaler 116 has an input terminalconnected to line 122. Switch 113 has first, second and controlterminals respectively connected to line 128, a line 134 and to line136. Threshold detector 118 outputs a signal SW_CONTROL on line 136.Switch 114 has first, second and control terminals respectivelyconnected to line 134, a ground bus, and line 136. Photodetector unit104 has a terminal 140 connected to line 122 to receive a voltage(V_(PD)) for reverse biasing its photodiode (not shown). Photodetectorunit 104 also has a terminal 142 connected to line 134 to receive avoltage (V_(AMP)) for powering the pre-amplifier (not shown). Powersequencing circuit 102 operates as described below in conjunction withFIG. 2.

[0016]FIG. 2 illustrates voltages (not to scale) at selected points ofpower sequencing circuit 102 (FIG. 1) during operation. The voltage atline 124 (i.e., signal POR) is represented by a waveform 201. Signal PORis a power-on reset signal generated by a circuit (not shown) externalto power sequencing circuit 102, typically when power is applied to thecircuit or when a user wants to reset system 100. The voltage at line122 (i.e., voltage V_(PD)) is represented by a waveform 203. The voltageat line 136 (i.e., signal SW_CONTROL) is represented by a waveform 205.The voltage at line 132 (i.e., voltage V_(AMP)) is represented by awaveform 207.

[0017] Referring to FIGS. 1 and 2, power-sequencing circuit 102 operatesas follows. Initially, in this embodiment, waveforms 201, 203 and 207are at a logic low level with waveform 205 (signal SW_CONTROL) at alogic high level. The logic low level of signal POR turns off (i.e.,opens) switches 111 and 112. Thus, the voltage sources providingvoltages V1 and V2 are isolated from lines 122 and 128.

[0018] When signal POR transitions to a logic high level (as indicatedby a rising edge 211 of waveform 201), switches 111 and 112 are turnedon (i.e. closed), thereby allowing the voltage sources providingvoltages V1 and V2 (also referred to herein as the V1 voltage source andthe V2 voltage source) to begin charging lines 122 and 128. The chargingof line 122 by the V1 voltage source is represented by a rising edge 213of waveform 203. In changing line 122, the V1 voltage source alsocharges capacitor 108. With switch 111 turned on, the voltage at line122 serves as voltage V_(PD) for photodetector unit 104 (FIG. 1).

[0019] As the V1 voltage source charges line 122 to voltage V1, scaler116 provides a scaled version of the voltage at line 122 (also referredto herein as the scaled voltage) to threshold detector 118. In thisembodiment, when the scaled voltage increases to reach the level of thethreshold voltage of threshold detector 118 (indicated by a dashed line215 in FIG. 2), threshold detector 118 outputs signal SW_CONTROL with alogic low level, as represented by a rising edge 217 of waveform 205.

[0020] The logic low level of signal SW_CONTROL turns on switch 113,which in turn allows the V2 voltage source to charge line 134 to voltageV2, as represented by a rising edge 219 of waveform 207. With switch 113turned on, the voltage at line 132 serves as voltage V_(AMP) forphotodetector unit 104 (FIG. 1).

[0021] The logic high level of signal SW_CONTROL also turns off switch114, thereby isolating the ground bus from line 134.

[0022] The use of threshold detector 118 to wait until voltage V_(PD)reaches a predetermined level advantageously delays the application ofvoltage V_(AMP) to photodetector unit 104 to ensure that voltage V_(PD)is greater than voltage V_(AMP), which in turn ensures that thephotodiode of photodetector unit 104 will not be forward biased duringthe power up sequence.

[0023] A power down sequence begins when signal POR transitions to alogic low level in response to a user turning off the system containingphotodetector unit 104 (FIG. 1) or when the external power sources areotherwise disconnected or fail. When signal POR transitions to a logiclow level (as indicated by a falling edge 221 of waveform 201), switches111 and 112 are turned off, thereby isolating the V1 and V2 voltagesources from lines 122 and 128. Thus, lines 122 and 128 begin todischarge, as indicated by falling edges 223 and 224 of waveforms 203and 207. However, because capacitor 108 has been charged duringpower-up, the voltage at line 122 drops at a rate slower than that ofthe voltage at line 134. This feature advantageously helps to ensurethat voltage V_(PD) is higher than voltage V_(AMP) during the power downsequence.

[0024] When the voltage at line 122 drops to a level that causes thescaled voltage (from scaler 116 in FIG. 1) to reach the level of thethreshold voltage (i.e., dashed line 215), then threshold detector 118transitions signal SW_CONTROL to a logic low level, as represented by afalling edge 227 of waveform 205. This logic low level turns on switch114 while turning off switch 113. Consequently, switch 113 isolates line134 from line 128, while switch 114 electrically connects line 134 tothe ground bus. Accordingly, the voltage at line 134 quickly drops tozero, as indicated by a portion 229 of the falling edge of waveform 207.This feature advantageously helps to further ensure that voltage V_(PD)remains higher than voltage V_(AMP) during the power down sequence.

[0025]FIG. 3 illustrates the relative timing of voltages V_(PD) andV_(AMP) provided by power sequencing circuit 102 (FIG. 1). The level ofvoltage V_(PD) during a power up and a power down sequence isrepresented by a waveform 303. Similarly, the level of voltage V_(AMP)is represented by a waveform 307, which is superimposed on waveform 303.As can be seen in FIG. 3, waveform 307 is always below waveform 303during both power up and power down. Since the anode and cathode of thephotodiode of photodetector 104 (FIG. 1) are respectively connected toreceive voltage V_(AMP) (waveform 307) and voltage V_(PD) (waveform303), the photodiode is advantageously not forward biased during bothpower up and power down.

[0026]FIG. 4 is a schematic diagram illustrating an implementation ofpower sequencing circuit 102 (FIG. 1), according to one embodiment ofthe present invention. In this embodiment, switches 111, 112 and 114 areimplemented using N-channel power MOSFETs (metal oxide semiconductorfield effect transistors). Switch 113 is implemented with a P-channelpower MOSFET. The term MOSFET is used herein to also include silicongate technologies. Although MOSFET switches are used in this embodiment,other embodiments may use different types of switching devices such as,for example, bi-polar transistors, relays, standard MOSFETs (as opposedto power MOSFETs), etc.

[0027] In addition, in this embodiment, scaler 116 is implemented with avoltage divider. As shown in the embodiment of FIG. 4, resistiveelements 401 and 401 are connected in series between line 122 and theground bus to implement scaler 116. Resistive elements can be anysuitable resistive element such as, for example, P-well resistors,MOSFETs biased in the linear or sub-threshold region, etc.

[0028] Still further, in this embodiment, threshold detector 118 isimplemented with a comparator 418. Comparator 418 compares the scaledvoltage with a reference voltage VREF. In one embodiment, theresistances of resistive elements 401 and 402 can be determined asfollows. In this exemplary embodiment, signal SW_CONTROL is designed totransition when voltage V_(AMP) is eleven volts. In addition, in thisembodiment, a standard 1.24 volt voltage reference is used to providevoltage VREF. Thus, using the voltage divider equation, resistiveelements 401 and 402 can have resistances of 88.8 KΩ and 11.2 KΩ (whichprovides a practical solution to the voltage divider equation).

[0029] The capacitance of capacitor 108 can be selected as follows. Inthis exemplary embodiment, line 22 has a resistance of 10Ω, and a timeconstant of 100 ms is desired for the delay. Thus, capacitor 108 has acapacitance of about 10000 μF to achieve this time constant. Thecapacitance of capacitor 108 can be selected based on the desired timeconstant and the loading and impedance of line 122 and photodetectorunit 104 (FIG. 1).

[0030] The elements of this implementation of power sequencing circuit102 are interconnected as described above in conjunction with FIG. 1,with some additional interconnections for comparator 418 implementingthreshold detector 118. More particularly, the gate terminals of theMOSFETS implementing switches 111-114 serve as the control terminals ofthe switches. Line 132 is connected to the node between resistiveelements 401 and 402.

[0031] Comparator 418 has its negative terminal connected to line 132,and has its positive terminal connected to a line 430 to receive areference voltage VREF. In this embodiment, voltage VREF serves as thethreshold voltage, and is provided by a voltage source or regulator thatis external to power sequencing circuit 102. This embodiment operates asdescribed above, with voltage VREF serving as the threshold voltage.

[0032] In an alternative embodiment, threshold detector 118 may beimplemented to have hysteresis. For example, threshold detector 118 maybe designed so that during a high-to-low transition of signal SW_CONTROL(i.e., a power up sequence), threshold detector 118 will cause signalSW_CONTROL to transition to a logic low level when voltage VPD is at arelatively low level (e.g., 11 volts). Consequently, switch 113 isturned ON after a relatively long delay into the power up sequence;thereby helping to ensure that voltage V_(PD) is greater than voltageV_(AMP) during the power up sequence.

[0033] On the other hand, during a low-to-high transition of signalSW_CONTROL (i.e., a power down sequence), threshold detector 118 isdesigned to cause signal SW_CONTROL to transition to a logic high levelwhen voltage V_(PD) is at a relatively high level (e.g., 11.5 volts). Asa result, switch 114 is advantageously turned on a relatively short timeinto the power down sequence to more quickly discharge line 134, therebyhelping to ensure that voltage V_(PD) is greater than voltage V_(AMP)during the power down sequence.

[0034] This hysteresis can be implemented in several ways. For example,signal SW_CONTROL may be fed back to a multiplexer (not shown) thanselects between two reference voltages to be provided on line 130. Inanother embodiment, signal SW_CONTROL may be fed back to a switch thatconnects/disconnects an additional resistive element to line 132 tochange the scaling of scaler 116, as a function of signal SW_CONTROL. Inyet another embodiment, threshold detector 118 may be replaced with aSchmitt trigger having its input terminal connected to line 132 toreceive an appropriately scaled voltage.

[0035] In another alternative embodiment, the conductivities of theMOSFETs implementing switches 113 and 114 are reversed, along with theinput terminals of threshold detector 118 (i.e., so that the positiveinput terminal is connected to line 132 and the negative input terminalis connected to line 130). In this way, waveform 205 (FIG. 2) will beinverted, and switches 113 and 114 will still turn on and off with theappropriate timing.

[0036] The above description of illustrated embodiments of theinvention, including what is described in the Abstract, is not intendedto be exhaustive or to limit the invention to the precise formsdisclosed. While specific embodiments of, and examples for, theinvention are described herein for illustrative purposes, variousequivalent modifications are possible within the scope of the invention,as those skilled in the relevant art will recognize.

[0037] These modifications can be made to the invention in light of theabove detailed description. The terms used in the following claimsshould not be construed to limit the invention to the specificembodiments disclosed in the specification and the claims. Rather, thescope of the invention is to be determined entirely by the followingclaims, which are to be construed in accordance with establisheddoctrines of claim interpretation.

APPENDIX A

[0038] William E. Alford, Reg. No. 37,764; Farzad E. Amini, Reg. No.P42,261; William Thomas Babbitt, Reg. No. 39,591; Carol F. Barry, Reg.No. 41,600; Jordan Michael Becker, Reg. No. 39,602; Todd M. Becker, Reg.No. 43,487; Lisa N. Benado, Reg. No. 39,995; Bradley J. Bereznak, Reg.No. 33,474; Michael A. Bernadicou, Reg. No. 35,934; Roger W. Blakely,Jr., Reg. No. 25,831; R. Alan Burnett, Reg. No. 46,149; Gregory D.Caldwell, Reg. No. 39,926; Andrew C. Chen, Reg. No. 43,544; Thomas M.Coester, Reg. No. 39,637; Donna Jo Coningsby, Reg. No. 41,684; FlorinCorie, Reg. No. 46,244; Dennis M. deGuzman, Reg. No. 41,702; Stephen M.De Klerk, Reg. No. P46,503; Michael Anthony DeSanctis, Reg. No. 39,957;Daniel M. De Vos, Reg. No. 37,813; Sanjeet Dutta, Reg. No. P46,145;Matthew C. Fagan, Reg. No. 37,542; Tarek N. Fahmi, Reg. No. 41,402;George Fountain, Reg. No. 37,374; Paramita Ghosh, Reg. No. 42,806; JamesY. Go, Reg. No. 40,621; Libby N. Ho, Reg. No. P46,774; James A. Henry,Reg. No. 41,064; Willmore F. Holbrow III, Reg. No. P41,845; Sheryl SueHolloway, Reg. No. 37,850; George W Hoover II, Reg. No. 32,992; Eric S.Hyman, Reg. No. 30,139; William W. Kidd, Reg. No. 31,772; Sang Hui Kim,Reg. No. 40,450; Walter T. Kim, Reg. No. 42,731; Eric T. King, Reg. No.44,188; Erica W. Kuo, Reg. No. 42,775; George Brian Leavell, Reg. No.45,436; Kurt P. Leyendecker, Reg. No. 42,799; Gordon R. Lindeen III,Reg. No. 33,192; Jan Carol Little, Reg. No. 41,181; Joseph Lutz, Reg.No. 43,765; Lawrence E. Lycke, Reg. No. 38,540; Michael J. Mallie, Reg.No. 36,591; Andre L. Marais, under 37 C.F.R. §10.9(b); Paul A. Mendonsa,Reg. No. 42,879; Clive D. Menezes, Reg. No. 45,493; Chun M. Ng, Reg. No.36,878; Thien T. Nguyen, Reg. No. 43,835; Thinh V. Nguyen, Reg. No.42,034; Dennis A. Nicholls, Reg. No. 42,036; Daniel E. Ovanezian, Reg.No. 41,236; Kenneth B. Paley, Reg. No. 38,989; Marina Portnova, Reg. No.P45,750; William F. Ryann, Reg. 44,313; James H. Salter, Reg. No.35,668; William W. Schaal, Reg. No. 39,018; James C. Scheller, Reg. No.31,195; Jeffrey Sam Smith, Reg. No. 39,377; Maria McCormack Sobrino,Reg. No. 31,639; Stanley W. Sokoloff, Reg. No. 25,128; Judith A.Szepesi, Reg. No. 39,393; Vincent P. Tassinari, Reg. No. 42,179; EdwinH. Taylor, Reg. No. 25,129; Lance A. Termes, Reg. No. 43,184; John F.Travis, Reg. No. 43,203; Joseph A. Twarowski, Reg. No. 42,191; Tom VanZandt, Reg. No. 43,219; Lester J. Vincent, Reg. No. 31,460; Glenn E. VonTersch, Reg. No. 41,364; John Patrick Ward, Reg. No. 40,216; Mark L.Watson, Reg. No. P46,322; Thomas C. Webster, Reg. No. P46,154; Steven D.Yates, Reg. No. 42,242; and Norman Zafman, Reg. No. 26,250; my patentattorneys, and Firasat Ali, Reg. No. 45,715; and Justin M. Dillon, Reg.No. 42,486; my patent agents, of BLAKELY, SOKOLOFF, TAYLOR & ZAFMAN LLP,with offices located at 12400 Wilshire Boulevard, 7th Floor, LosAngeles, Calif. 90025, telephone (310) 207-3800, and Alan K. Aldous,Reg. No. 31,905; Edward R. Brake, Reg. No. 37,784; Ben Burge, Reg. No.42,372; Jeffrey S. Draeger, Reg. No. 41,000; Cynthia Thomas Faatz, RegNo. 39,973; John N. Greaves, Reg. No. 40,362; Seth Z. Kalson, Reg. No.40,670; David J. Kaplan, Reg. No. 41,105; Peter Lam, Reg. No. 44,855;Charles A. Mirho, Reg. No. 41,199; Leo V. Novakoski, Reg. No. 37,198;Thomas C. Reynolds, Reg. No. 32,488; Kenneth M. Seddon, Reg. No. 43,105;Mark Seeley, Reg. No. 32,299; Steven P. Skabrat, Reg. No. 36,279; HowardA. Skaist, Reg. No. 36,008; Gene I. Su, Reg. No. 45,140; Calvin E.Wells, Reg. No. P43,256, Raymond J. Werner, Reg. No. 34,752; Robert G.Winkle, Reg. No. 37,474; and Charles K. Young, Reg. No. 39,435; mypatent attorneys, of INTEL CORPORATION; and James R. Thein, Reg. No.31,710, my patent attorney with full power of substitution andrevocation, to prosecute this application and to transact all businessin the Patent and Trademark Office connected herewith.

APPENDIX B Title 37, Code of Federal Regulations, Section 1.56 Duty toDisclose Information Material to Patentability

[0039] (a) A patent by its very nature is affected with a publicinterest. The public interest is best served, and the most effectivepatent examination occurs when, at the time an application is beingexamined, the Office is aware of and evaluates the teachings of allinformation material to patentability. Each individual associated withthe filing and prosecution of a patent application has a duty of candorand good faith in dealing with the Office, which includes a duty todisclose to the Office all information known to that individual to bematerial to patentability as defined in this section. The duty todisclosure information exists with respect to each pending claim untilthe claim is cancelled or withdrawn from consideration, or theapplication becomes abandoned. Information material to the patentabilityof a claim that is cancelled or withdrawn from consideration need not besubmitted if the information is not material to the patentability of anyclaim remaining under consideration in the application. There is no dutyto submit information which is not material to the patentability of anyexisting claim. The duty to disclosure all information known to bematerial to patentability is deemed to be satisfied if all informationknown to be material to patentability of any claim issued in a patentwas cited by the Office or submitted to the Office in the mannerprescribed by §§1.97(b)-(d) and 1.98. However, no patent will be grantedon an application in connection with which fraud on the Office waspracticed or attempted or the duty of disclosure was violated throughbad faith or intentional misconduct. The Office encourages applicants tocarefully examine:

[0040] (1) Prior art cited in search reports of a foreign patent officein a counterpart application, and

[0041] (2) The closest information over which individuals associatedwith the filing or prosecution of a patent application believe anypending claim patentably defines, to make sure that any materialinformation contained therein is disclosed to the Office.

[0042] (b) Under this section, information is material to patentabilitywhen it is not cumulative to information already of record or being madeor record in the application, and

[0043] (1) It establishes, by itself or in combination with otherinformation, a prima facie case of unpatentability of a claim; or

[0044] (2) It refutes, or is inconsistent with, a position the applicanttakes in:

[0045] (i) Opposing an argument of unpatentability relied on by theOffice, or

[0046] (ii) Asserting an argument of patentability.

[0047] A prima facie case of unpatentability is established when theinformation compels a conclusion that a claim is unpatentable under thepreponderance of evidence, burden-of-proof standard, giving each term inthe claim its broadest reasonable construction consistent with thespecification, and before any consideration is given to evidence whichmay be submitted in an attempt to establish a contrary conclusion ofpatentability.

[0048] (c) Individuals associated with the filing or prosecution of apatent application within the meaning of this section are:

[0049] (1) Each inventor named in the application;

[0050] (2) Each attorney or agent who prepares or prosecutes theapplication; and

[0051] (3) Every other person who is substantively involved in thepreparation or prosecution of the application and who is associated withthe inventor, with the assignee or with anyone to whom there is anobligation to assign the application.

[0052] (d) Individuals other than the attorney, agent or inventor maycomply with this section by disclosing information to the attorney,agent, or inventor.

What is claimed is:
 1. A circuit, comprising: a first input terminalcoupleable to a first voltage source; a second input terminal coupleableto a second voltage source; a first output terminal coupleable to aphotodetector unit; a second output terminal coupleable to thephotodetector unit a capacitor coupled to the first output terminal; afirst switch coupled to the first input terminal and to the first outputterminal, wherein the first switch to open during a power down sequence;a second switch coupled to the second input terminal and the secondoutput terminal; a third switch coupled to the output terminal and asupply rail; and a threshold detector having an input lead coupled tothe first output terminal and an output lead coupled to the second andthird switches, wherein the threshold detector to cause second and thirdswitches to open and close, respectively, during the power down sequenceas a function of the voltage at the first output terminal.
 2. Thecircuit of claim 1, further comprising a fourth switch, wherein thesecond input terminal and the second switch are coupled through thefourth switch, the fourth switch to open during the power down sequence.3. The circuit of claim 1, further comprising a scaler, wherein thefirst output terminal and the input lead of the threshold detector arecoupled through the scaler.
 4. The circuit of claim 3, wherein thescaler comprises a voltage divider.
 5. The circuit of claim 1, whereinthe threshold detector further to cause the second and third switches toclose and open, respectively, during a power-up sequence.
 6. The circuitof claim 5, wherein the first switch is closed during the power upsequence.
 7. The circuit of claim 1, wherein the threshold detectorcomprises a Schmitt trigger.
 8. The circuit of claim 1, wherein thethreshold detector comprises a comparator, the comparator having anotherinput lead coupled to receive a reference voltage.
 9. The circuit ofclaim 1, further comprising a feedback circuit coupled to the thresholddetector, wherein the feedback circuit to cause the threshold detectorto have hysteresis.
 10. The circuit of claim 1, wherein the second andthird switches each comprise a power metal-oxide-semiconductor fieldeffect transistor (MOSFET).
 11. The circuit of claim 10, wherein thepower MOSFET of the second switch has a conductivity opposite that ofthe third switch.
 12. A circuit, comprising: a first input terminalcoupled to a first voltage source; a second input terminal coupled to asecond voltage source; a first output terminal coupleable to aphotodetector unit; a second output terminal coupleable to thephotodetector unit a capacitor coupled to the first output terminal; afirst switch coupled to the first input terminal and to the first outputterminal; a second switch coupled to the second input terminal and thesecond output terminal; a third switch coupled to the output terminaland a supply rail; and switch control means for causing the second andthird switches to open and close, respectively, during a power downsequence as a function of a voltage at the first output terminal. 13.The circuit of claim 12, further comprising a fourth switch, wherein thesecond input terminal and the second switch are coupled through thefourth switch.
 14. The circuit of claim 12, further comprising a scalercoupled to the first output terminal and the switch control means. 15.The circuit of claim 14, wherein the scaler comprises a voltage divider.16. The circuit of claim 12, wherein the switch control means furtherfor causing the second and third switches to close and open,respectively, during a power-up sequence.
 17. The circuit of claim 16,wherein the first switch is opened and closed during the power up andpower down sequences, respectively.
 18. The circuit of claim 12, whereinthe switch control means comprises a Schmitt trigger.
 19. The circuit ofclaim 12, wherein the switch control means further for comparing areference voltage to a voltage dependent on the voltage provided by thefirst voltage source.
 20. The circuit of claim 12, wherein the switchcontrol means has hysteresis.
 21. A method, comprising: charging acapacitor coupled to a first input terminal of a photodetector unitduring a power up sequence; interrupting a flow of power from a firstvoltage source providing a first voltage to the first input terminal ofa photodetector unit during a power down sequence; interrupting a flowof power from a second voltage source providing a second voltage to asecond input terminal of the photodetector unit during the power downsequence, wherein the second voltage is smaller than the first voltage;detecting when the capacitor discharges to a predetermined thresholdduring the power down sequence; and connecting the second input terminalto a ground rail during the power down sequence.
 22. The method of claim21, wherein a comparator is used to detect when the capacitor hasdischarged to the predetermined threshold.
 23. The method of claim 21,wherein detecting when the capacitor has discharged to a predeterminedthreshold comprises: providing a scaled voltage that is a function ofthe voltage of the capacitor; and comparing the scaled voltage with areference voltage, the reference voltage being a function of thepredetermined threshold.
 24. The method of claim 23, wherein the scaledvoltage is provided by a voltage divider connected to the outputterminal.
 25. An apparatus, comprising: a capacitor coupleable to afirst input terminal of a photodetector unit; means for charging thecapacitor during a power up sequence of the photodetector unit; meansfor interrupting a flow of power from a first voltage source providing afirst voltage to the first input terminal of a photodetector unit duringa power down sequence of the photodetector unit; means for interruptinga flow of power from a second voltage source providing a second voltagethat is smaller than the first voltage to a second input terminal of thephotodetector unit during the power down sequence; means for detectingwhen the capacitor has discharged to a predetermined threshold duringthe power down sequence; and means for connecting the second inputterminal to a ground rail during the power down sequence.
 26. Theapparatus of claim 25, wherein the means for detecting comprises acomparator.
 27. The apparatus of claim 25, wherein the means fordetecting comprises: means for providing a scaled voltage that is afunction of the voltage of the capacitor; and means for comparing thescaled voltage with a reference voltage, the reference voltage being afunction of the predetermined threshold.
 28. A system, comprising: afirst input terminal coupleable to a first voltage source; a secondinput terminal coupleable to a second voltage source; a photodetectorunit having a first node and a second node; a capacitor coupled to thefirst node; a first switch coupled to the first input terminal and tothe first node, the first switch to open during a power down sequence; asecond switch coupled to the second input terminal and the second node;a third switch coupled to the second node and coupleable to a supplyrail; and a threshold detector having an input lead coupled to the firstnode and having an output lead coupled to the second and third switches,wherein the threshold detector to cause the second and third switches toopen and close, respectively, during the power down sequence as afunction of a voltage at the first node.
 29. The system of claim 28,further comprising a fourth switch, wherein the second input terminaland the second switch are coupled through the fourth switch, the fourthswitch to open during the power down sequence.
 30. The system of claim28, further comprising a voltage divider, wherein the first outputterminal and the input lead of the comparator are coupled through thevoltage divider.